Diagnostic memory dumps can be performed to observe the various memory contents to aid in understanding the behavior of a chip at certain target cycles. However, current methods to observe the entire memory contents can be difficult and time consuming, and can be costly in terms of the silicon area needed for the diagnostic circuit elements.
Some integrated circuits or chips include a memory built-in self test (BIST) which is a mechanism that permits the chip to test its memory. Some integrated circuits also include a debugger interface, for example a Joint Test Action Group (JTAG) interface. Debugging systems can communicate with chips through the debugger interface to perform operations like single stepping and break pointing to debug various components on the chip.
It would be desirable to leverage and reuse the BIST and debugger interface for diagnostic memory dumps.